SBIR/STTR Research Award
A NEW MACHINE ARCHITECTURE FOR STRUCTURAL ANALYSIS
Award amount
$49,873Program and phase
SBIR · Phase IAward year
1991Award details
- Awarding agency
- National Aeronautics and Space Administration
- Branch
- Not reported
- Recipient company
- Space Tech Corp
- Proposal award date
- Not reported
- Contract end date
- Not reported
- UEI
- Not reported
- Solicitation number
- Not reported
- Topic code
- Not reported
Research abstract
THE PROJECT INVOLVES DEVELOPMENT OF A FAST, NOVEL, SCIENTIFIC WORKSTATION FOR SOLVING AEROPROPULSION SYSTEM STRUCTURES WITH CYCLIC SYMMETRY EXHIBITING NONLINEAR RESPONSE IN HIGH TEMPERATURES. AN ENGINEERING STUDY WILL MAP EFFICIENT ALGORITHMS ONTO NEW PARALLEL ARCHITECTURE THAT IS EXTENSIBLE ACROSS BOTH THE SIMD AND MIMD DESIGN PARADIGM. A SIGNIFICANT FEATURE OF THE APPROACH IS THE COUPLING OF THE SAME COMPUTATIONAL KERNEL TO SEVERAL PROCESSING ELEMENTS SO THAT TRUE PARALLEL COMPUTING WITHOUT USUAL DATA-PARTITIONING OVERHEAD OCCURS. A FULLY PARALLEL, SINGLE INSTRUCTION/CLOCK CROSSBAR ASIC IS TO BE IMPLEMENTED FOR THE DYNAMICALLY RECONFIGURABLE ARCHITECTURE. THIS CAN NOW BE ACHIEVED ONLY THROUGH RECENT VLSI DISCOVERIES WITH ASIC DEVICES. BECAUSE THE COMPUTER HARDWARD "GLUE LOGIC" HAS SHRUNK, PHYSICAL BOARDS AND BACKPLANES HAVE ALSO REDUCED TO MAKE ECONOMIC DESIGNS AT 200 MHZ CLOCKS FEASIBLE. THE PROJECT INVOLVES DEVELOPMENT OF A FAST, NOVEL, SCIENTIFIC WORKSTATION FOR SOLVING AEROPROPULSION SYSTEM STRUCTURES WITH CYCLIC SYMMETRY EXHIBITING NONLINEAR RESPONSE IN HIGH TEMPERATURES. AN ENGINEERING STUDY WILL MAP EFFICIENT ALGORITHMS ONTO NEW PARALLEL ARCHITECTURE THAT IS EXTENSIBLE ACROSS BOTH THE SIMD AND MIMD DESIGN PARADIGM. A SIGNIFICANT FEATURE OF THE APPROACH IS THE COUPLING OF THE SAME COMPUTATIONAL KERNEL TO SEVERAL PROCESSING ELEMENTS SO THAT TRUE PARALLEL COMPUTING WITHOUT USUAL DATA-PARTITIONING OVERHEAD OCCURS. A FULLY PARALLEL, SINGLE INSTRUCTION/CLOCK CROSSBAR ASIC IS TO BE IMPLEMENTED FOR THE DYNAMICALLY RECONFIGURABLE ARCHITECTURE. THIS CAN NOW BE ACHIEVED ONLY THROUGH RECENT VLSI DISCOVERIES WITH ASIC DEVICES. BECAUSE THE COMPUTER HARDWARD "GLUE LOGIC" HAS SHRUNK, PHYSICAL BOARDS AND BACKPLANES HAVE ALSO REDUCED TO MAKE ECONOMIC DESIGNS AT 200 MHZ CLOCKS FEASIBLE.
Technology keywords
Not reported