Germanium-Free Strained-SOI Wafers

"We propose to combine the technologies of SOI manufacture with strain-inducing wafer bonding to produce Strained-Si On Insulator (SSOI) wafers. Optimizing this new Strained-Silicon-on-Insulator will increase carrier mobilities by a factor of at least x3,lower the band gap by 20%, and reduce operating power of existing technologies by a factor of x4. The above performance enhancements are over and above the enhancements arising from the thin Si layer and the insulating substrates. Our method of fabricationenables treatment for radiation hardness. IBM has announced their commitment to straining silicon as a viable alternative to `scaling' in the quest for higher performance. Their method of obtaining strained silicon involves expensive techniques includingSi/Ge heterostructures fabrication. The presence of Ge severely limits IC processing. By contrast our method would not require customized processing or new device architectures. Intel is now poised to go mainstream with SOI chips taking SOI chipproduction out of the niche market. Intel is showing interest in our technology. These major developments open great potential for the proposed combination. Ultra-fast, mainstream silicon-based electronics will be enabled using current technology. Speedincreases of x3 will be made possible using existing processing technology. This increase in speed is accompanied by a decrease in operating voltage by a factor of x4. Power dissipation will