ADVANCED A/D MONOLITHIC CHIP ARCHITECTURE DESIGNS FOR WIDE DYNAMIC RANGE AND GIGASAMPLE CONVERSION RATES

MONOLITHIC IMPLEMENTATION OF DATA CONVERTERS AT THE 8 BIT, 1 GIGA SAMPLES PER SECOND LEVEL ARE CONSIDERED A HIGH PRIORITY ITEM FOR MANY MILITARY AND COMMERCIAL APPLICATIONS, RANGING FROM THE MMIC/VHSIC INTERFACE TO RADAR SIGNAL PROCESSING, ELECTRONIC COUNTERMEASURES, AND INSTRUMENTATION. THESE HIGH SAMPLING RATES MANDATE THE USE OF VERY HIGH SPEED ARCHITECTURES OBTAINED VIA EXPENSIVE PROCESSING TECHNOLOGIES SUCH AS HETEROJUNCTION BIPOLAR TRANSISTORS (HBTS). ANALOG TO DIGITAL (A/D) CONVERTERS THAT ARE KNOWN TO WORK AT THE HIGHEST SPEED TYPICALLY INVOLVE A STRAIGHT FLASH ARCHITECTURE, PRECEDED BY A DIODE-BRIDGE SAMPLE AND HOLD (S/H) CIRCUIT. HOWEVER, IT IS DIFFICULT TO ATTAIN SINGLE-CHIP IMPLEMENTATIONS FOR CONVERTERS WITH RESOLUTION GREATER THAN 8 BITS BECAUSE THESE TOPOLOGIES INVOLVE A LARGE DEVICE COUNT AND LARGE POWER DISSIPATION. FURTHERMORE, MULTI-CHIP REALIZATIONS YIELD DEGRADED PERFORMANCE AND INCREASED POWER DISSIPATION COMPARED TO MONOLITHIC APPROACHES, DUE TO OVERHEAD INCURRED WHEN DRIVING SIGNALS BETWEEN CHIPS. THE PURPOSE OF THIS RESEARCH IS TO INVESTIGATE MORE EFFICIENT ARCHITECTURES IN TERMS OF CHIP SIZE, POWER CONSUMPTION, AND 8-BIT RESOLUTION AT 1 GIGASAMPLES PER SECOND USING NEW ADVANCED PROCESS TECHNOLOGIES SUCH AS HBTS. THE RESULTS OF THE INNOVATION PROPOSED HEREIN CAN BE USED FOR MANY MILITARY AND COMMERCIAL APPLICATIONS RANGING FROM THE MMIC/VHSIC INTERFACE TO RADAR SIGNAL PROCESSING, ELECTRONIC COUNTER MEASURES, AND INSTRUMENTATION.