SBIR/STTR Research Award
SBIR Phase I: High-Precision Timing Devices for Research and Industry
Award amount
$305,000Program and phase
SBIR · Phase IAward year
2025Award details
- Awarding agency
- National Science Foundation
- Branch
- Not reported
- Recipient company
- Main Engineering LLC
- Proposal award date
- 2025-03-21
- Contract end date
- 2026-06-30
- UEI
- GSX3L6CQDVR4
- Solicitation number
- NSF 24-579
- Topic code
- S
Research abstract
The broader impact/commercial impacts of this Small Business Innovation Research (SBIR) Phase I project is in developing timing devices with increased performance and capability. These timing devices, capable of picosecond accuracy (a trillionth of a second), enable nuclear physics research, light detection and ranging, and medical imaging. This project will develop a time-to-digital converter (TDC) with unique features and the capability to operate in harsh environments. A TDC is an electronic device that measures time intervals with extremely high precision and converts the measured time into a digital value. TDCs are widely used in applications requiring precise timing, such as LIDAR, high-energy physics, medical imaging, and communications. The market opportunities and the competitive advantage are secured through an architecture that overcomes the limitations of current TDC implementations. The developed TDCs will be semiconductor chip based that will be fabricated domestically and introduced to three primary markets: nuclear physics, spacecraft instrumentation, and medical imaging devices.
This Small Business Innovation Research (SBIR) Phase I project is a high-availability TDC that features zero dead-time, unlimited multi-hits, picosecond accuracy, and a dedicated calibration circuit. A proof-of-concept already exists, and a prototype application-specific integrated circuit is ready for fabrication. Phase I addresses research and development of hardware and software and overall robustness to withstand high radiation and cryogenic temperatures. This will be achieved through an iterative design methodology between logic design, transistor design, and transistor layout, each in their respective software environment. At the conclusion to Phase I, the primary goal is to have a second prototype ready to send to a chip fabrication facility. This prototype will include new features of the design, as well as radiation hardening. The radiation hardening will all
Technology keywords
Not reported