Scalable Accelerators And Interfaces For Hpc System

This feasbility effort is directed toward analyzing, designing, implementing, and demonstrating standard interfaces for the popular general purpose Intel 860 XR based scalable accelrator array board from several vendors (e.g., SKY Computers). For example, the widely used SKY embedded processor accelerator product family is scalable from 1 to 16 processors (1.28 Gflop) per VME 9U board, with up to 8 board per chassis (128 processors) and up to 8 such chassis in a system, providing over 100 Glops of computing capability at a cost of about $5 million, and power consumption of less than ten kilowatts. however, to effectively uitlize this SUN host based cost-effective, real time embedded super-accelerator, it is esentiual that it be interfaced at a baord level, to enable (hardware based) computational load balancing, with one of several alternate interface standards pertaining to: 1) super-computers/parallel disk arrays, 2) input sensors (e.g., multiple CCD cameras, multiple microphones), and 3) large (e.g., 2048 x 2048 pixels) SBGA format screens. Specific standard interfaces to be demonstrated are: 1) super computer HIPPI (ANSI X3T9.3), 2) multichannel (e.g., 3) RS170 (video), and 3) multiple SBGA (low cost displays. Early prototying experiments have demonstrated the feasibility of capturing incoming video with less than a 1/10 (i.e., 3-1/3 millisec) frame pipeline delay, thereby enabling "near real time" multiple video sensor processing. We anticipate a corresponding level of success in implementing above-mentioned scalable I/O interfaces. ANTICIPATED BENEFITS: The proposed interfaces will enalbe both military and commercial users to cost-effectively implement HPCC grade systems, both in the (multimedia) laboratory, as well as on real-time embedded applications on-board (e.g., air, surface, ground) moving platforms. This effort will eliminate the constraints faced by current users, in terms of the availability of diverse/mulitiple sensor input, high pixel count display output, and an HPCC compatible interface.