Body Worn Graphic Image Generator for Simulator Based Training

Size, cost, and potential obsolescence are the key concerns in this design for a deployable body-worn image generator for driving a twenty megapixel head mounted display. To minimize the size and cost, a parallel architecture is adopted with modules at thechip level rather than at the PC level. The design effort focuses on the development of a bus architecture that minimizes the design time needed to produce a module from the latest COTS graphics accellerator chip. Further substantial cost and size ispossible from using a digitally inset high-resolution-area of interest. This approach takes advantage of the human eye actually having high resolution in a small area centered on the direction of view. Digitally insetting the high resolution area overcomesthe lag problems associated with past systems that depended upon mechanical servomechanisms. Feasibility of adapting an eye-tracker to a wide field-of-view HMD is an object of the Phase I research. Developing a parallel chip architecture design isexpected to save two-thirds of the cost and size of a parallel PC approach. Developing a bus design suitable for single-chip modules may allow advancement of as much as two six-month cycles of COTS graphics accelerator chips. The development of anarea-of-interest approach, however, would yield a full factor of ten savings in the required capacity of the visual system while still providing eye-limited resolution to the user. The smaller and less expensive the visual system, the greater its potentialability to be deployed in both military and commercial training applications.