Superconducting Digital RF Memory

Superconducting A/D converters at multi-GHz clock speeds with 4-8 bit resolution open possibilities for full simultaneous 2-20 GHz coverage DRFMs. However, high speed Superconducting memories do not offer the required density for DRFM applications. Sierra Monolithics/TRW team proposes the development of a random access memory scheme with speed and density needed for Superconducting DRFM (S-DRFM) applications. The memory proposed is a hybrid of the high speed SFQ memory and high density Cryogenic CMOS. The Superconducting SFQ circuits are used to handle incoming data from ADC, memory management, RAM sense amplifiers, and data stream reconstruction. The cryogenic CMOS circuits are used for high density memory cells, line decoders, and high voltage drivers. Thus, the speed and complexity barriers for microwave digital memory are overcome. The Phase I effort will be devoted to the architectural design and simulation of the Superconducting SFQ multiplexer and demultiplexer, memory management and superconducting sense amplifiers for bit detection. The hardware demonstration of the key components will be performed in Phase II.