SBIR Phase I: HW-Accelerated Verification with TestBench Caching and Reduced Design Compilation

This SBIR Phase I project addresses issues related to verication and debugging of application specic integrated circuits (ASICs) and systems on chip (SOCs) and proposes a novel solution to drastically improve efficiency and performance of design verication. The design verication already dominates the overall design development time and negatively impacts the designer productivity and product's time to market. The proposed method is based on a novel technology, called testbench caching, which reduces by the several orders of magnitude the HW/SW communication overhead. It is combined with the technique that also reduces the need for frequent and time intensive design compilation, and increased signal visibility, essential for fast hardware debugging. Over 100 times improvement is expected w.r.to traditional simulation, and 10-20 times w.r.to traditional simulation acceleration. This project will result in the development of a prototype system to validate the above claims. By accelerating the verication and providing efficient debugging facility the proposed solution will substantially shorten time to market for ASIC and SOC designs. Designers productivity will increase, lowering product development and labor costs. The proposed system methodology will have a signicant, positive commercial impact and will contribute to the growth of the verication systems market.