Ultra-Low-Power, Charge-Mode Digital Processors (Q_DOT Research Proposal 1349)

Q-DOT proposes to develop ultra-low-power charge-mode digital processors for use in advanced packaging technologies. Initial estimates project a reduction factor of 10 to 30 in power dissipation when state-of-the-art CMOS is replaced with advanced, charge-mode logic. For example, a 32-bit serial shift built with 1um design rules and operating at 200 MHz and 5V power will dissipate 5 mW in charge mode logic and 180 mW in CMOS. While the 36:1 factor can not be maintained in more complex functions, a 10:1 ratio appears to be feasible. During Phase I, meaningful processor architectures will be developed in charge-mode logic. Their performance will be simulated. In Phase II proof-of-concept processor elements will be built.