High-Performance Network Interface for Advanced Avionics Architectures

Group 16 Research and Development proposes to research and demonstrate the feasibility of developing new low-latency, high-throughput network interfacing elements that will permit next-generation avionics systems to exploit high-performance computing and communications in an efficient, scalable, portable, and interoperable manner with independence between applications and interconnects. The interfacing elements will consist of a novel hardware interface between the processor/memory bus and gigabit network, and lightweight channel software working with the hardware in support of distributed and parallel applications. The hardware interface will be designed to achieve on the order of processor-memory bandwidth or interconnect throughput, whichever is less, to support a high-performance commercial interconnect standard such as Scalable Coherent Interface, Fibre Channel, or Serial Express, and to support a high-performance processor architecture such as UltraSPARC, PowerPC, or Pentium-II. The software interface will be designed to provide lightweight communications, interoperability, and portability across message-passing and shared-memory, and support distributed and parallel processing mechanisms including CORBA-compatible object request brokering and POSIX-compatible, low-latency multithreading. A new and unique integrated simulation environment will be used to model the processor, network, and software architectures with high fidelity to match performance characteristics in order to achieve optimum throughput, latency, and system cost.