Developing a Reconfigurable On-Line Modeling Platform

DESCRIPTION (provided by applicant): This proposal is being sent in response to NIMH PA-00-118. The objective of this proposal is to begin the commercialization process of a high performance reconfigurable signal-processing platform that will perform real-time on-line analysis of large-scale multi-channel data streams for data-driven neural simulations and modeling. The platform will be used to aid the discovery process where the cooperative neural encoding schemes through which sensory information is represented and transmitted within a nervous system will be uncovered. The system will enable real-time decoding of the neural information streams, and will enable experimental perturbation of the encoded information while the neural signals are in transit between peripheral and central processing stages. This will provide an unprecedented degree of interactive control in the analysis of neural function, and could lead to major insights into the biological basis of neural computation. The aim of this Phase I proposal is to construct a computation node using high performance field programmable gate arrays (FPGA) to be used in a data-driven modeling platform and to develop the associated software necessary to implementing neural models (mapping algorithms to hardware) efficiently in high end FPGA devices to enable real-time modeling & simulations. This will involve developing prototype boards comprised of Xilinx's Virtex-II Pro FPGAs with adequate communication bandwidth between nodes to ensure real-time performance. Several implementation techniques will be explored to discover the most efficient method of implementing neural modeling algorithms in hardware. These methods include: 1.) Using Mathwork's Matlab/Simulink and Xilinx's System Generator to map Simulink block diagrams to hardware. 2.) Using Xilinx's FORGE compiler to translate JAVA code to hardware. 3.) Using Celoxica's C Compiler to translate C code to hardware. 4.) Developing and embedding custom neural microprocessors in FPGAs.