Multi-Gigabit OS Bypass System for Grid Computing

76151-Upon transmitting or receiving messages, classical network interface cards generate an interrupt to the operating system kernel, and thus to the host processor, which must service the interrupt. However, as grid-based scientific computing within DOE networks approach 10 ¿ 40 Gigabits per second, this procedure could tie down the host processor with interrupt latency. Therefore, new operating system (OS) bypass systems are needed to provide a direct interface from the application to the Network Interface Card (NIC). This project will develop a modular, scalable architecture, capable of handling bandwidths from 10 to 40 Gigabits per second, while providing true OS Bypass performance. In Phase I, the feasibility of the architecture will be determined through simulations of system integrity and data flow. For proof of concept, a new code will be constructed and tested within a 10 Gbps network processor development environment. Commercial Applications and Other Benefits as described by the awardee: The new OS bypass system should have application to cluster and Grid systems using wide area networks, as well as enterprise servers, professional workstations, blade servers, redundant arrays of independent disks, storage area networks, and communications systems manufacturers.