SBIR/STTR Research Award

AN 8-BIT 2 GHZ INTEGRATING ANALOG-TO-DIGITAL CONVERTER FOR COHERENT-ON-RECEIVE UWB (ULTRAWIDE BANDWIDTH) RADAR

Award identifier 4db377866d4c7382ade9f4b2f784d646b500a414506f238933f728b87e381d27Awarding agency Department of Defense · Army

Award amount

$71,832

Program and phase

SBIR · Phase I

Award year

1990

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Award details

Awarding agency
Department of Defense
Branch
Army
Recipient company
Mei Research
Proposal award date
Not reported
Contract end date
Not reported
UEI
Not reported
Solicitation number
Not reported
Topic code
Not reported

Research abstract

RADAR DETECTION OF WEAK TARGETS IN THE PRESENCE OF A HIGH LEVEL OF CLUTTER NECESSITATES AN ULTRA WIDE BANDWIDTH ANALOG-TO-DIGITAL CONVERTER (ADC) WITH SUFFICIENT RESOLUTION. THIS PROPOSAL PRESENTS A TECHNICAL APPROACH AND SYSTEM ARCHITECTURE FOR AN 8-BIT, 2 GHZ FULL SCALE BANDWIDTH INTEGRATING ADC TO SATISFY THIS NEED. ADDITIONALLY, THE ADC WILL BE DRIVEN BY A CLOCK SIGNAL WHICH CAN BE SYNCHRONIZED TO A TRIGGER PULSE WITH A RESOLUTION OF +/0.5 PICOSECOND. SUCH AN ADC WOULD FACILITATE THE DEVELOPMENT OF A COHERENTON-RECEIVER UWB (ULTRA WIDE BANDWIDTH) RADAR RECEIVERS. WHAT IS PROPOSED IS A "FLASH"ADC ARCHITECTURE, WITH FAST ACT (ACOUSTIC CHARGE TRANSPORT) SAMPLERS ON THE FRONT-END, AND SLOWER, COMMERCIALLY AVAILABLE 8-BIT ADCS ON THE BACK-END. TWO EMBODIEMENTS ARE DESCRIBED.ONE NECESSITATES USING THE ACT DEVICE AS A SERIAL OF PARALLEL CONVERTER IN ADDITION TO A SAMPLER AND REALIZES 8 BITS OF ADC SYSTEM RESOLUTION. THE OTHER DOES NOT REQUIRE ANY SERIAL TO PARALLEL SHIFTING BUT ACHIEVES ONLY 6 BITS OF RESOLUTION.

Technology keywords

Not reported

Agency intelligence

Department of Defense

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