Reconfigurable Task Processor

In Phase I of this SBIR, PicoDyne developed and simulated an architecture for Reconfigurable Task Processor (RTP). The RTP combines a Field Programmable Gate Array (FPGA) with a processing unit on a single chip. This combination allows for compact electronics for space applications. A 32-bit processing unit, compliant with the SPARC Version 8 architecture, was chosen for implementation due to its high processing capability, compact area utilization, and the many readily available Real-Time Operating Systems and development software. The processor design is licensed to PicoDyne under the GNU LGPL license. The European Space Agency developed the LEON2 SPARC core, and made it available for space electronics developers. It was developed with System-on-Chip implementations in mind, with an expandable AMBA standard on-chip interface for use with on-chip peripherals. We have architected the RTP with an array of reconfigurable logic as the primary peripheral. It is connected to the processor bus, and may be directly configured by software for many applications. The reconfigurable logic may be used simply as decode logic for off-chip peripherals, saving board space, or as a co-processor for data filtering, data compression, or communications protocol encoding and decoding. In Phase II, the RTP will be completely configured and simulated, following an ASIC design flow, then implemented in a CMOS silicon chip. Using PicoDyne's proven Radiation Tolerant and Ultra-Low-Power design techniques and processes, this capable device will enable NASA programs to accomplish more with electronics with less power and reduced board area requirements, and may be enabling technology for missions such as NanoSats.