GALLIUM ARSENIDE ON SILICON FOR MICROELECTRONIC AND OPTOELECTRONIC INTEGRATED CIRCUITS

THE GROWTH OF DEVICE QUALITY, LARGE AREA GAAS EPITAXIAL LAYERS ON SILICON SUBSTRATES IS RECOGNIZED AS AN IMPORTANT TECHNOLOGICAL DEVELOPMENT. THE QUALITY OF HETEROEPITAXIAL LAYERS OF GAAS ON SILICON ARE LIMITED BY GAAS-SI LATTICE MISMATCH AND THERMAL COEFFICIENT MISMATCH. THE DEFECT DENSITY OF THE GAAS EPILAYER IS DIRECTLY RELATED TO THE INTERFACE AREA. OUR LABORATORIES HAVE DEMONSTRATED A VIABLE GAAS-SI GROWTH TECHNIQUE: SELECTIVE LIQUID PHASE EPITAXY, SLPE. THIS APPROACH ENHANCES THE EPILAYER QUALITY SINCE THE LATERAL OVERGROWTH REGION IS SHIELDED FROM DEFECTSORIGINATING AT THE INTERFACE. THE SUBSTRATE IS PREPARED BY PLACING A SILICON DIOXIDE LAYERON THE SILICON AND OPENING A SELECTIVE PATTERN IN THE OXIDE USING PHOTOLITHOGRAPHY. THE NUCLEATION VIAS WILL BE FIVE MICRONS WIDE AND ONE HUNDRED MICRONS LONG, PLACED ON FIFTY TO ONE HUNDRED MICRON CENTERS. AFTER NUCLEATION INTHE VIAS, LATERAL OVERGROWTH WILL YIELD DEVICE QUALITY GAAS ON SILICON. DIRECT CONTACT BETWEEN THE GAAS AND SILICON WILL BE LIMITED, WHICH WILL LIMIT LATERAL TENSION AND CONFINE DISLOCATION PROPAGATION TO THE VIA AREA.