SBIR/STTR Research Award
A PARALLEL PROCESSOR FOR SIMULATING MANIPULATORS AND OTHER MECHANICAL SYSTEMS
Award amount
$443,756Program and phase
SBIR · Phase IIAward year
1990Award details
- Awarding agency
- National Aeronautics and Space Administration
- Branch
- Not reported
- Recipient company
- Electronic Associates Inc.
- Proposal award date
- Not reported
- Contract end date
- Not reported
- UEI
- Not reported
- Solicitation number
- Not reported
- Topic code
- Not reported
Research abstract
SIMULATION IS AN IMPORTANT TOOL IN THE DESIGN AND REAL-TIME CONTROL OF MECHANICAL SYSTEMS, SUCH AS MANIPULATORS AND ACTUATORS. AS SUCH SYSTEMS BECOME MORE COMPLEX, THE COMPUTATIONAL BURDEN GROWS, AND IT BECOMES INCREASINGLY DIFFICULT TO MAINTAIN A REAL-TIME SOLUTION. THIS PROPOSAL DESCRIBES AN INNOVATIVE PARALLEL COMPUTER ARCHITECTURE FOR THE SIMULATION OF MECHANICAL SYSTEMS. THE ARCHITECTURE EVOLVED FROM THE ANALOG COMPUTER, RATHER THAN FROM THE VON NEUMANN DIGITAL COMPUTER. AS SUCH, IT OFFERS A CONSIDERABLE IMPROVEMENT IN SPEED: PRELIMINARY ESTIMATES INDICATE IT IS 10 TO 100 TIMES FASTER THAN CONVENTIONAL ARCHITECTURES. THE DESIGN HAS BEEN VALIDATED FOR A SMALL VERSION OF THE ARCHITECTURE, CONSISTING OF A SINGLE MODULE (A SMALL NUMBER OF TIGHTLY-COUPLED PROCESSORS). THE KEY OBJECTIVE OF PHASE I IS TO EVALUATE A LARGER VERSION, WITH SEVERAL MODULES, TO INCREASE SOLUTION SPEED. THE PRINCIPAL PHASE I EFFORT IS TO MODIFY THE EXISTING SCHEDULING ALGORITHM TO INCLUDE SUCH MULTI-MODULE SYSTEMS, AND TO EVALUATE THE EXTENDED ARCHITECTURE BY PROGRAMMING SEVERAL APPLICATIONS, OBTAINING DETAILED SPEED COMPARISONS WITH CONVENTIONAL ARCHITECTURES. THE PRINCIPAL PHASE II EFFORT IS TO CONSTRUCT A PROTOTYPE TO VERIFY THE PHASE I TIMING ASSUMPTIONS.
Technology keywords
Not reported