Design Automation for Low Power Digital Electronics

Power dissipation is becoming critically important in large scale systems particularly with the increasing need for portability. Research into design techniques for reducing power has been hindered by the inability of design tools to include power dissipation in the early stages of the design process. A method to incorporate nodal activity into Algorithm Specific Architecture Programmable (ASAP) VHDL chip generators has been established. This capability will enable the development of a correlation between power dissipation and a weighted sum of nodal activity. This will result in the ability to quickly evaluate the power dissipation of a system while it is still described at a technology independent, high level of abstraction. We then propose to investigate using this capability to enable the transition of two low power design approaches from academic concepts to useful techniques as part of a next generation low power design methodology. We will investigate a reduced voltage approach which maintains throughput by pipelining and a self-timed approach which is data driven (asynchronous) instead of clock driven. In addition to reduced power, attributes associated with a top down VHDL-based methodology will be preserved: reduced time-to-market, technology independence, technology retargeting/upgrading, and design re-use.