SBIR/STTR Research Award
Development of an Advanced Avionics Processor
Award amount
$0Program and phase
SBIR · Phase IAward year
2003Award details
- Awarding agency
- Department of Defense
- Branch
- Air Force
- Recipient company
- CPU TECHNOLOGY, INC.
- Proposal award date
- Not reported
- Contract end date
- Not reported
- UEI
- Not reported
- Solicitation number
- Not reported
- Topic code
- Not reported
Research abstract
The objective is to design a modern very high performance microprocessor that will 1) execute existing MIL-STD-1750A software at the binary level, without modification or recomplilation, 2) solve the memory addressing and performance limitations of the1750A, and 3) permit new avionics software to be developed that will utilize the characteristics of the new instruction set architecture. Additionally, the new microprocessor will be designed in such a way that generation to generation obsolescence ofimplementation technology will no longer be an issue.The technical approach addresses this problem by first using three new processor technology inventions to describe a new ISA that is fully backward compatible with the 1750A ISA at the binary level, solves 1750A memory and performance problems, and hasevery instruction formally verified. Phase II will design and simulate a modern high performance microprocessor that will implement the new ISA defined in Phase I.
Technology keywords
Not reported