GENERAL PURPOSE HARDWARE TEST SET FOR RAPID VERIFICATION OF LOW ERROR -FALSE ALARM- RATES IN DIGITAL COM AND RADAR

Real time hardware channel simulators are critical elements in the design, debug and testing of communication systems. Signatron has for over 20 years been a pioneer and leading developer of channel simulators for a wide range of special purposes, including radar, sonar, and Satellite, microwave, troposcatter, HF, and meteor scatter communications. The objective of the proposed effort is to provide a new hardware simulation capability that can, in effect, operate faster than real time by using Importance Sampling (IS) techniques to artificially emphasize error-generating events. Signatron has used IS in many radar and communications computer simulations and has identified the key issues affecting faithfulness of the simulation, particularly the difficult issues relating to the hardware simulation. While IS simulation is relatively simple for memoryless systems, it is less efficient, and generally more complicated, for the most common case of systems with memory. A novel approach for adapting the IS simulator to a system, and solving the problems with unknown delay with memory, is proposed. The Phase I effort will study the implementation issues and a validation methodology. A general purpose additive noise simulator design will be developed and the extension to multiplicative (fading) systems will be evaluated using IS techniques already developed at Signatron. The specification for the Phase II advanced development will be developed to meet the widest range of military and commercial applications possible.