NEXT-AGAIN-GENERATION RADIATION HARD CMOS

We proposed a simple wafer scale method to leap frog current CMOS technology. The slow-down in CMOS scaling is limited by technology difficulties and by economics. In tooling up for .13-micron technology, the jump from .18-micron is costing $10 billionis equipment alone, plus accompanying expenses of redesign and module formulation. The net effect of this massive capital investment is to replace 1.2GHz with 2.9GHz computers. In the same arena we can take .018-micron technology and get 5GHZ with lessthan $5m development costs and perform the same advance (x4) on 13-micron technology to get over 11Ghz using the same equipment and technology. Our tooling cost will be $500k. Our technique uses mechanical strain and is inexpensive. It is applied afterconventional IC fabrication is completed, taking full advantage of all the positive attributes of silicon (low cost, high transistor count, high reliability etc.) Providing potential performance figures more normally associated with materials such asGaAs. Initial results indicate performance levels associated with halving the channel length. Benefits include reducing short channel effects and contact potentials. Hence quadrupling the effective performance is possible for silicon ICs with minimalprocess development. Our technique will extend the effective limit of scaling in microelectronics via changing the properties of silicon. Cost comparison in terms of realizing the next generation of mainstream computer clock times: Industry: 1.3 to 2.9GHz, equipment along; $10,000,000,000. Our Technology: 1.3 to 5 Ghz, equipment; $500000. Industry: 0.13-micron to sub 0.1-micron ... at present not technically possible. Out Technology 1.3 to 11 GHz, $500,000.