SBIR/STTR Research Award

Design and development of the LID - LGAD Integrated Digitizer

Award identifier 9a151c06172e8909d3738a58e60fdea150e3752e1d4c5bc4ae856aec11d5e350Awarding agency Department of Energy

Award amount

$206,425

Program and phase

SBIR · Phase I

Award year

2025

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Award details

Awarding agency
Department of Energy
Branch
Not reported
Recipient company
NALU SCIENTIFIC, LLC
Proposal award date
2025-02-18
Contract end date
2026-02-17
UEI
ZFYUKU9F8TQ4
Solicitation number
DE-FOA-0003417
Topic code
C59-27d

Research abstract

Next generation HEP experiments require detection of many interactions in very small volumes with unprecedented timing at the picosecond level and spatial precisions approaching 10𝜇m using advanced sensor arrays such as low-gain avalanche diodes. Existing readout approaches use time-to-digital and time-over-threshold based measurements. In this Phase I project, we will alternatively pursue an improved approach based on full waveform digitization that allows for precise measurement of charge to achieve sub-pixel spatial resolution, while allowing correction of systematic effects due to e.g. pile-up, sensor aging, radiation and other environmental factors. Mainstream continuous ADC systems are impractical for readout of very small pitch sensor arrays given the severe design and operational constraints of space, cost, power and performance typical of deployments in large detectors such as at the LHC, and existing waveform sampling devices are not scaled to the small sizes necessary. The processing of full waveform information on-chip additionally avoids the bottleneck of large data transfers, a very significant advantage compared to other solutions. We propose to design and make commercially available a high channel density System-on-Chip capable of interfacing directly with state-of-the-art AC-coupled low-gain avalanche diode arrays, which will perform autonomous digitization, feature extraction, and data fusion to deliver high timing and spatial precision, and will implement internal calibration and monitoring circuitry. The design will be implemented as a compact module capable of easy integration for the design of large detectors with arbitrary geometries and will use a simple standardized readout interface. Based on previous architectural studies and existing prototype measurements, a complete full-chip architecture (64-81 channels) will be studied and a corresponding design will be completed. This device can be used by scientists in high-energy and nuclear physics experiments for fast analog data acquisition from small pitch detector arrays. It has applications in PET imaging through bundling with photomultiplier arrays. We anticipate being able to sell the device as an OEM manufacturer, provide associated design services or license it to a larger device manufacturer due to the low cost and low-power design, which will give us a competitive edge.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

33 SBIR/STTR records share this UEI (2016–2025). Reported award amounts total $14,748,717. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Energy, National Aeronautics and Space Administration, Department of Health and Human Services, Department of Defense, Department of Commerce

Agency intelligence

Department of Energy

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