Low Temperature CMOS Integratable Ferroelectric Thin Film Process

Multi-component dielectric thin films suitable for solid state electronics have been deposited using various conventional chemical vapor deposition (CVD) techniques, including organometallic CVD, plasma enhanced CVD, and low pressure CVD. However, these approaches are difficult to integrate with standard silicon IC processing of ferroelectric DRAM and NVFRAM attributed to high deposition temperatures, >600¿C, damaging the underlying transistor circuitry. In contrast, MicroCoating Technologies' (MCT) innovative, patented, open atmosphere Combustion CVD process can be used to deposit device grade ferroelectric films on wafers at <500¿C suitable for IC device processing. The CCVD process is described in detail herein. Rensselaer Polytechnic Institute has measured the electronic properties of test capacitors of 300 nm CCVD BST and SrTiO3 films deposited on Si/Ti/Pt wafers at ~400¿C substrate temperature. They display quality comparable to state-of-the-art CVD films, including uniformity, density, high permittivity, high dielectric breakdown strength, and low leakage current. MCT has also used the CCVD process to deposit epitaxial ferroelectric films on single crystal MgO substrates with great success. We propose to build on this initial achievement to apply the CCVD technique for commercially viable deposition of high performance dielectrics for integration with dynamic random access memory (DRAM) and non-volatile ferroelectric memory (NVFRAM) fabrication. Ba1-xSrxTiO3 (BST) and SrTiO3 (STO) will be the primary candidate materials for DRAM due to their high dielectric constants. Pb(ZrxTi1-x)O3 (PZT) and SrBi2Ta2O9 (SBT) are valued for NVFRAM applications owing to their high switchable polarization. In Phase I, we will grow high quality thin films with desired substrate temperatures < 500¿C and evaluate their physical, chemical, and electronic properties. The CCVD process and materials will be optimized for integrated circuit applications and reproducibility will be demonstrated. This will lay a solid groundwork for Phases II in which we will scale up and automate the CCVD process for reliable, cost effective processing of semico