SBIR/STTR Research Award

Application Specific Electronic Design Synthesis

Award identifier a529c14a8ee4afcc3806a4e03ac6653275ee390691e0aa1e4b1839d5eca32c04Awarding agency Department of Defense · Air Force

Award amount

$501,196

Program and phase

SBIR · Phase II

Award year

1994

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Award details

Awarding agency
Department of Defense
Branch
Air Force
Recipient company
Dqdt
Proposal award date
Not reported
Contract end date
Not reported
UEI
Not reported
Solicitation number
Not reported
Topic code
Not reported

Research abstract

The overall goal of this program is the development of tools for rapid synthesis of common classes of electronic systems. DQDT's approach is to create generators which synthesize application specific VHDL descriptions of systems from high-level specifications. These generators can then leverage readily available and constantly improving VHDL based CAD tools for simulation, gate level synthesis, and mask level synthesis. By synthesizing at the VHDL level, these generators have complete independence from the chip fabrication vendor, the CAD tool vendor, and the hardware platform. Also, the inherent technology retargeting and upgrading capability of this approach shields new systems from early obsolescence due to rapidly improving chip technology. Through a novel use of standard VHDL constructs, the proposed generators offer the user control over the amount and degree of bit-level pipelining and over the implementation style of arithmetic elements. These features significantly broaden the speed-area solution space beyond existing gate level logic manipulation methods. A library of generators will be created which are oriented around common signal processing functions such as filters, convolvers, adaptive operators, and transforms. The end product of the Phase I effort will be a complete implementation of a digital filter generator tool to evaluate the efficacy of the proposed approach.

Technology keywords

Not reported

Agency intelligence

Department of Defense

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