Multi-chip Integration

The goal of this research project is to determine the viability of an interconnect and probing technology which could be used to test and burn-in unpackaged semiconductors at system level speed, and at operating frequency, with voltage and with temperature margins verified. The focus of the research will be to address directly the most costly limitation to widespread MCM use; the problem of readily determining "known good die" (KGD). The scope of the Phase I research is to investigate the viability of an integrated interconnect technology designed to contact and test one to several unpackaged die. A significant challenge is to develop the ability to probe the pads without damaging the bond or compromising device realiability. The selected interconnection and probing technology must be suitable for use in both room temperature and thermal cycling; and instatic high temperature environments up to 165 degrees C. The technical challendges vary depending on whether the integrated circuit device is destined to be attached to the next level package by wire bonding, TAB or a form of flip chip attachment. ANTICIPATED BENEFITS: Acsist believes that it will be able to commercialize a proven interconnect method for contracting one to several unpackaged die without damage to the attachment pads which is suitable for use in a wide range of temperature environments for the realization of the KDG concept.