NUMERICAL ANALYSIS ON MASSIVELY PARALLEL PROCESSING COMPUTERS

AIR FORCE MISSIONS REQUIRE COMPUTERS OF IMMENSE SUSTAINED CPU/IO BANDWIDTHS, NOT CURRENTLY AVAILABLE. THESE NEW ARCHITECTURES INVOKE GREATER DEMANDS ON THE COMPILATION PHASE, BUT CURRENT COMPILERS LACK THE CAPABILITIES TO GENERATE "PARALLEL" CODE WITHOUT CONSIDERABLE HUMAN EFFORT. A META-COMPILER IS PROPOSED FOR PARALLEL MACHINES. A MAJOR INNOVATION IS THE EFFECTIVE CAPTURE OF DATA/INSTRUCTION PIPELINING AND PARALLELISM FOR THE CODE GENERATION, OPTIMIZATION, AND FIRMWARE COMPACTION PHASES . A DEVELOPMENT EFFORT IS PROPOSED TO EMBODY THESE THEORETIC ADVANCES INTO THE PARALLEL PROCESSOR COMPILER FOR CFD CODE. EXTENSIONS TO THE COMPILER TECHNOLOGY ARE PROPOSED THAT WILL EFFECT COMPILATION OF VERY DIVERSE MACHINES, INCLUDING SYSTOLIC, PARALLEL, AND VECTOR ARCHITECTURES. AN EXCITING POTENTIAL NOW EXISTS TO COMPILE CODE FOR NEURAL NET MACHINES. PHASE I OF THE EFFORT WILL DETERMINE IF A MASSIVELY PARALLEL COMPUTER ARCHITECTURE CAN BE USED TO SIGNIFICANTLY SPEED UP THE NUMERICAL SOLUTION OF THE REYNOLDS-AVERAGED NAVIER-STOKES AND EULER EQUATIONS. SPACE TECH PROPOSES TO QUANTIFY THE RELATIVE MERITS OF SIMD AND MIND ARCHITECTURES AND, IF APPROPRIATE, OTHER ARCHITECTURES THAT WOULD BE ADVANTAGEOUS FOR CFD SOLUTIONS. SPACE TECH WILL ALSO IDENTIFY THE OPTIMUM NUMBER AND/OR ARRANGEMENT OF PROCESSORS AND COMPARE MAXIMUM THEORETICAL COMPUTER SPEEDS WITH REALISTIC SPEEDS FOR PRACTICAL PROBLEMS. THE PHASE II EFFORT WILL BE TO DEVELOP OR MODIFY A REYNOLDS-AVERAGED NAVIER-STOKES OR EULER CODE THAT WOULD BE OPTIMIZED TO RUN ON AN EXISTING MACHINE THAT UTILIZES THE COMPUTER ARCHITECTURE DETERMINED IN PHASE I TO SHOW THE GREATEST PAYOFF.