Pulse-Synchronized Serializer/De-Serializer-Based Interconnect

72293S03-I High-Energy Physics (HEP) experiments at the Large Hadron Collider utilize more than 90 million signal channels among different types of detectors with total aggregate data rates of 40 Terabytes per second. A high-speed, high-density, low-power interconnect, compatible with standard HEP bus technology such as VME or FASTBUS, is needed for the collection of real-time data. The interconnect would use dedicated high-capacity data links for on-line trigger and data acquisition systems that would reduce the data volume to about 100 Megabytes per second. This project will develop a novel Pulse Synchronized Serializer/De-serializer-based (PSSD) optical interconnect as a building block for real-time monitoring systems for large-scale sensor arrays. Phase I will prove the feasibility of the PSSD concept, using a bench-prototype demonstration and a transistor-level simulation study. The transmitter and the receiver architecture will be thoroughly evaluated. Phase II will implement a PSSD link prototype capable of supporting multi-Terabits per second data rates in a Wavelength Division Mutiplexing (WDM) backplane environment. Commercial Applications and Other Benefits as described by awardee: The PSSD-based interconnect should lead to a new performance class of large-scale computer and communication systems utilizing optical chip-to-chip and board-to-board system busses, thereby reducing power dissipation and latency while adding virtually unlimited data throughput.