SBIR Phase I: Hermetic Micropackaging Applying Wafer-Level and Chip-Scale Integration

This Small Business Innovation Research Phase I project addresses packaging techniques for MEMS/NEMS components and systems. Applying wafer-level and chip-scale approaches new designs will allow for hermetic encapsulation of sensitive structures, as well as simple, multi-functional electrical, microfluidic, optical and thermal interconnection of system components. This project will demonstrate feasibility of a method to package electronic components in such a way that a) high frequency performance is optimized; b) cost is minimized; c) the integrity of the components are protected both during packaging and over life; d) application flexibility is maintained. The basic process steps will be demonstrated and prototypes developed for wafer-level chip-scale packaging for optical components using proprietary techniques for temporary wafer bonding of pre-thinned wafers; formation of through-substrate vias, along with insulation and metallization of the vias; and joining by solder or other methods. The proposed packaging techniques allow for a variety of devices to be placed in a miniature sealed cavity, having provision for maintenance of vacuum over life. Also in conjunction with inkjet printing methods, a single via design may be adapted to fluidics, optics or thermal dissipation. Wafer-level and chip-scale-packaging offers critical advantages of miniaturization, cost reduction, and performance and reliability enhancements. These are, in fact, the historical and future drivers for most of the semiconductor industry. In addition to mainstream semiconductor applications, the approach offers unique solutions for devices such as inertial grade navigation instruments, where performance and reliability enhancements may be of utmost importance.