Computationally Efficient Parallel Codes, Algorithms or Tools for Computational Prototyping (Parallelization of Analog..

This research will define, and establish the feasibility and commercialization potential of, a parallelized analog hardware description language (HDL) and simulator. The language will consist of extensions to the VHSIC Hardware Description Language (VHDL), and will by synergistic to current analog HDL development and standardization efforts. The technology shall be developed from existing analog HDL technology and parallel computing VHDL speedup techniques, being designed under other ARPA/government-sponsored HPCC projects as well as under commercial initiatives. The purpose of the language and simulator is to provide effective, high-speed simulation capability to support designers of large and complex mixed-signal computing and communications systems. The program objectives are to (1) define the language and simulator - as extensions to the existing technologies, (2) evaluate and demonstrate the feasibility - by implementing a language subset and executing a definitive simulation test case upon low, medium, and high-performance parallel computers, and (3) assess the commercialization potential - through liaison with commercial vendors of VHDL-based electronic design automation (EDA) tools. The Phase I products will be the substative language and simulator definition, the experimentally-determined feasibility assessment, and a preliminary commercialization plan based upon marketability assessments from current marketplace participants, to form the Phase II foundation. ANTICIPATED BENEFITS: An immediate benefit will be enabling HDL-assisted electro-optical designs critical to HPCC initiatives. Broadly, the technology allows mixed signal-designers to apply high-speed simulation. Commercial opportunities include all mixed-signal designers as well as any analog system designers (thermal, mechanical, fluid, etc.)