AN INTELLIGENT SCSI INTERFACE FOR FASTBUS

AN INTELLIGENT INTERFACE BETWEEN FASTBUS AND THE ANSI STANDARD SMALL COMPUTER SYSTEM INTERFACE (SCSI) BUS WILL BE INVESTIGATED. THE PHASE I OBJECTIVE WILL BE A DETAILED HARDWARE DESIGN OF SUCH AN INTERFACE, PLUS AN ANALYSIS OF THE SOFTWARE REQUIRED TO RELIEVE FASTBUS PROGRAMMERS OF ANY SCSI RESPONSIBILITY. THE PROPOSED INTERFACE WILL IMPLEMENT THE SCSI WIDE DATA TRANSFER OPTION, PROVIDING A 32 BIT WIDE DATA PATH. A TRANSFER RATE OF 40 MBYTES PER SECOND WILL BE POSSIBLE, USING THE SYNCHRONOUS PROTOCOL AND TIMING SPECIFIED IN THE SCSI II STANDARD. THE INTERFACE WILL FUNCTION AS A FASTBUS MASTER OR SLAVE, AND AS EITHER AN SCSI INITIATOR OR TARGET. AS AN INITIATOR,IT WILL PERMIT ANY OTHER FASTBUS MASTER TO ACCESS ANY SCSI PERIPHERAL, OR ANOTHER PROCESSOR ACTING AS A SCSI PROCESSOR TYPE DEVICE. IT WILL ALSO BE PROGRAMMED TO RESPOND AS A SCSI TARGET OF THE PROCESSOR TYPE, PERMITTING A HOST COMPUTER TO INITIATE COMMUNICATION WITH ANY FASTBUS DEVICE. IT WILL BE POSSIBLE FOR A FASTBUS DEVICE TO INTERRUPT ANOTHER PROCESSOR TYPE DEVICE ON THE SCSI BUS, AND FOR AN SCSI PROCESSOR TO ACCESS ANY FASTBUS INTERRUPT SERVICE DEVICE. IT IS PROPOSED TO CREATE THE WIDE DATA PATH USING A PARALLELARRAY OF COMMERCIALLY AVAILABLE SCSI PROTOCOL CHIPS, SUITABLY SYNCHRONIZED. AN ON-BOARD MICROPROCESSOR WILL PERFORM LOW LEVEL CONTROL OF THE CHIPS SELECTED. AT A HIGHER LEVEL IT WILL IMPLEMENT ALL MANDATORY SCSI MESSAGES AND COMMANDS, PLUS THE COMMANDS SPECIFIED FOR A VARIETY OF SCSI DEVICES THAT MIGHT BE USED WITH FASTBUS.