A Library Based Integrated Hardware/Software Codesign Environment (P47LBHSC)

JRS is proposing to provide a complete integrated hardware/software codesign environment that provides visual programming capabilities and reusable, plug-in hardware and software parts libraries. The system is referred to as the MultiProcessor Compilation System (MCS). It is based on the JRS IDAS toolset, which provides currently a large portion of the functionality ultimately required for the MCS. The MCS incorporates PGM, Ada 9X, and VHDL technology. IDAS is currently in use on a number of major Government programs, including ARPA ASEM, ARPA RASSP, and ARPA DICE. The MCS extended IDAS will be integrated with the Army currently existing Architecture Schema, Architecture Description Language, and Repository Tools to the extent feasible. In Phase I, JRS will demonstrate existing tools and identify, define, and specify the additional functionality needed to meet the Government objectives. Detailed documentation, including an Implementation Plan for Phase II, will be prepared and delivered. In Phase II, the MCS will be developed in accordance with the Specifications and Plans from Phase I.