SBIR/STTR Research Award
One-Size-Fits-All Hardened Electronic Design and Test Platform
Award amount
$70,000Program and phase
SBIR · Phase IAward year
2003Award details
- Awarding agency
- Department of Defense
- Branch
- Missile Defense Agency
- Recipient company
- QUICKFLEX INC.
- Proposal award date
- Not reported
- Contract end date
- Not reported
- UEI
- LDM7N1HHNRX7
- Solicitation number
- Not reported
- Topic code
- Not reported
Research abstract
Modern FPGA design methodology can aid engineers in the creation of circuit architectures capable of detecting radiation-induced failures and reconfiguring on-the-fly. However, verification tools are not presently available to validate the hardened design.QuickFlex proven, standardized, system-level management of FPGAs will be used to create a hardware testing platform combined with ASC's design optimization software. Benchmark testable designs will validate the system. The innovative system can reconfigurehardware to enable rapid correction of errors due to transient single-event upset (SEU). During Phase I we will specify the requirements for the design software, the test platform and the integration process to create a
Technology keywords
Not reported
Other awards by this recipient
Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.
- ElectronicVeil -- Advanced Security Architectures for Mobile Computing Platforms
- FlexDuo – An FPGA Accelerated, Flexible Execution Mission Processing
- ElectronicVeil - Advanced Security Architectures for Mobile Computing Platforms
- FlexDuoFPGA Accelerated, Flexible Execution Mission Processing Architecture
- A Standardized Development Suite for Decision Engines
Research funding history
25 SBIR/STTR records share this UEI (2003–2020). Reported award amounts total $10,275,616. Reported amounts are not federal obligations.
Phases: Phase I, Phase II
Agencies: Department of Defense, National Aeronautics and Space Administration, Department of Energy