Development of an Advanced Avionics Processor

Problem: All of the currently defined Instruction Set Architectures (ISAs) are faced with obsolescence. The 1750A has fallen behind in the areas of performance and amount of addressable memory. Newer processor meet today's requirements but have no clear path for avoiding obsolescence in the future and necessitate the abondonment of the existing support software base. Objective: Develop an ISA that will remain competitive and compatible for over 256 generations and will support the existing 1750A software base. The ISA will be implemented with the development of a high performance, multi-issue, multi-generational microprocessor. Approach: Phase I involves modeling the 3 inventions and simulating them using proprietary design environment to apply concepts. Model other functions and simulate as necessary in order to perform trade-offs. Generate specifications derived from work. Phase II involves generating and verifiying a fully operational model of a high performance microprocessor based on the ISA through system simulation of the SEAFAC suite and other diagnositcs. Phase III includes the detailed design and prototyping of the microprocessor.