MONOLITHICALLY INTEGRATED DETECTOR ARRAYS

THIS PHASE I PROJECT WILL DEVELOP A DETECTOR TECHNOLOGY FOR TRACKING PARTICLES CLOSE TO THE BEAM PIPE IN NEW GENERATION ACCELERATOR EXPERIMENTS. HIGH SPATIAL RESOLUTION, HIGH SPEED DATA READOUT, COMPACT SIZE, LOW POWER, AND RADIATION HARDNESS WILL BE ACHIEVED BY INCORPORATING A HIGH RESISTIVITY, DETECTOR GRADE, 300 MUM THICK WAFER PATTERNED WITH P(+) DETECTOR ELEMENTS INTO THE RADIATION HARDENED, SUBMICRON BOND AND ETCHBACK SILICON ON INSULATOR (BESOI) PROCESS. A PROCESS WILL BE DEVELOPED TO FABRICATE INTERCONNECTS BETWEEN THE BURIED DETECTOR JUNCTION ELEMENTS AND READOUT CIRCUITRY FABRICATED IN THE SOI FILM. EXPERIMENTS WILL BE PERFORMED TO EVALUATE THE IMPACT ON THE DETECTORS OF USING THE RADIATION HARDENED COMPOSITE METAL OXIDE SEMICONDUCTOR (CMOS)/BESOI PROCESS TO FABRICATE THE READIUT CIRCUITRY. PHASE I WILL DEMONSTRATE A CIRCUIT DESIGN/LAYOUT INTERFACE TO TRANSLATE DETECTOR READOUT CIRCUITRY INTO THE INTEGRATED DETECTOR PROCESS. A DETECTOR PRE-AMPLIFIER CIRCUIT LAYOUT WILL BE MODIFIED TO BE CONSISTENT WITH THE CMOS/BESOI DESIGN RULES. SPICE (SIMULATION PROGRAM WITH INTEGRATED CIRCUIT EMPHASIS) SIMULATIONS WIL BE PERFORMED ON BOTH THE BULK AND SOI VERSIONS OF THE CIRCUIT TO VERIFY AND COMPARE PERFORMANCE SPECIFICATIONS.