OPEN ARCHITECTURE FOR ELECTRONIC DESIGN AND SUPPORT TOOLS

WE PROPOSE TO DEVELOP A SET OF FORMAL ABSTRACT DATA MODEL WHICH WILL CREATE AN OPEN ARCHITECTURE FOR ELECTRONICS COMPPUTER-AIDED DEIGN, EVALUATION, TEST, AND DIAGNOSIS TOOLS. OUR ARCHITECTURE IS MODELED AFTER THE HIGHLY SUCCESFUL OPEN SYSTEM INTEROCNNECTION REFERENCE MODEL WHICH HAS BECOME THE INTERNATIONAL STANDARD FOR COMMUNICATION SYSTEMS. THE OSI MODEL SPECIFIES DATA AND OPERATIONS ONLY AT THE INTERFACES BETWEEN SEVEN HIERARCHICALLY ORGANIZED LEVELS. SYSTEMS ADHERING TO THOSE INTERFACES CAN INTERCOMMUNICATE EVEN THOUGH, INTERNALLY, THEY ARE ENTIRELY DIFFERENT. FOR OUR OPEN ARCHITECTURE WE PROPOSE A COMPONENT LEVEL, DEPENDENCY LEVEL, AMBIGUITY GROUP LEVEL, TEST VECTOR LEVEL, FAULT TREE LEVEL, FAULT DICTIONARY LEVEL, AND DIAGNOSTIC RULES LEVEL. MANY NEW TOOLS ARE BEING DEVELOPED TO AID IN THE DESIGN IMPLEMENTATION, AND SUPPORT OF ELECTRONIC SYSTEMS. IF SUCCESSFUL, THE PROPOSED OPEN ARCHITECTURE WOULD ENABLE SUCH TOOLS TO BE USED TO VALIDATE THE RESULTS OF OTHER TOOLS BY ENABLING BOTH TOOL SYSTEMS TO USE THE SAME INPUT AND PRODUCE OUTPUTS IN THE SAME FORMAT. THIS VERIFICATION AND VALIDATION CAPABILITY WOULD HELP INCREASE THE RELIABILITY OF TODAY'S INCREASINGLY COMPLEX ELECTRONIC SYSTEMS. THE PROPOSED PHASE I EFFORT WILL FOCUS ON THE DEPENDENCY, AMBIGUITY GROUP, AND TEST VECTOR LAYERS OF THE ARCHITECTURE.