SBIR/STTR Research Award

Single Electron Field Effect Transistor (SEFET) Memory on SOI (silicon on insulator) by MBE and in Situ Oxidization

Award identifier 11e0adafb1a5a60aec4086bae2eb6948004b481c65e5d711715040bda990423fAwarding agency Department of Defense · Defense Advanced Research Projects Agency

Award amount

$99,000

Program and phase

SBIR · Phase I

Award year

1997

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Award details

Awarding agency
Department of Defense
Branch
Defense Advanced Research Projects Agency
Recipient company
NANODYNAMICS-88, INC.
Proposal award date
Not reported
Contract end date
Not reported
UEI
Not reported
Solicitation number
Not reported
Topic code
Not reported

Research abstract

Single electron FET (SEFET) has the advantage of nano-scaled devices size, fast charging time and quantized charging voltage, with much lower power. However, the technical requirement and large threshold voltage fluctuation, shift the performance at room temperature resulting in difficulties in its integration. We propose a SEFET with crystalline Si floating gate and channel on EPSOI (epitaxy silicon on insulator) mainly fabricated by MBE with in situ oxidization. This can not only significantly relax the fabrication requirements, improve the performance of SEFET at room temperature, but also, more importantly, provide a more uniform threshold voltage to make this new type of device suitable for integration. The SEFET basically includes control-gate/floating-gate, nano-channel and insulator between gate/channel and channel/substrate. The process for the device is very complicated and highly costly. The silicon channel was typically fabricated on SOI, formed by oxygen ion implantation, followed by deposition of polysilicon layer for floating gate. The difficulty involved in the grain size control of polysilicon affects the performance of the floating gate charge, and ion implantation results in oxygen inclusions and annealing at high temperature. However, our newly developed technology Si/O superlattice is capable of being incorporated into a MBE process of the construction for device structure envisioned in this endeavor.

Technology keywords

Not reported

Agency intelligence

Department of Defense

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