COMPILER TECHNOLOGY FOR SCALABLE PARALLEL COMPUTERS

THE WORLD OF PARALLEL PROCESSORS IS SEEING A SIGNIFICANT LAG BETWEEN HARDWARE AND SOFTWARE. THE PROBLEM FACED BY PARALLEL PROGRAMMERS, AKIN TO THAT FACED BY EARLY ASSEMBLER PROGRAM WRITERS, IS THE LACK OF ADEQUATE COMPILERS, WHICH WOULD INSULATE PROGRAMMERSFROM THE LOW-LEVEL ARCHITECTURAL DETAILS, CONTRIBUTING TO RAPID PROGRAM SYNTHESIS AND PORTABILITY. THE FIRST STEPS TOWARD THIS GOAL HAVE BEEN TAKEN BY THE DO-LOOP PARALLELIZING COMPILERS, USED PREDOMINANTLY FOR PARALLEL FORTRAN. A MORE GENERALIZED APPROACH, FOR POINTER-BASED LANGUAGES, IS PRESENTED IN THE CURARE WORK. IN THIS PROPOSAL WE INTENDTO INCORPORATE BOTH THESE TECHNIQUES AND FURTHER THIS GOAL THROUGH THE USE OF OUR COMPILER EXPERTISE. WE SHALL INVESTIGATE THE USE OF DECLARATIONS TO AID THE COMPILER IN AUTOMATIC DETECTION OF PARALLELISM. FURTHER, WE WILL PIPELINE AND PARALLELIZE THE COMPILER ITSELF, THEREBY FURTHER INCREASING SOFTWARE PRODUCTIVITY. IT IS CONTENDED THAT AN EFFICIENT MACHINE-INDEPENDENT INTERFACE THAT RELIEVES PARALLEL PROGRAMMERSOF HAVING TO DEAL WITH ARCHITECTURAL DETAILS WILL GREATLY ENHANCE THEWRITING OF PARALLEL PROGRAMS, REGARDLESS OF APPLICATION. ANTICIPATED BENEFITS/POTENTIAL COMMERCIAL APPLICATIONS - ACHIEVING THE GOALS IN PHASE I WILL PROVIDE A FOUNDATION FOR FURTHER COMPILER PARALLELIZATION, PERFORMANCE TUNING, AND INTEGRATION OF MORE PARALLELIZED PROGRAMMINGPRODUCTIVITY TOOLS (SUCH AS DECLARATIONS) IN PHASE II. GIVEN THAT ANEFFICIENT PARALLEL COMPILER WOULD BE THE SINGLE MOST IMPORTANT FACTORIN BRIDGING THE GAP BETWEEN PARALLEL HARDWARE AND SOFTWARE ADVANCES, ALL APPLICATIONS USING PARALLEL LANGUAGES WOULD BENEFIT FROM THIS WORK, INCLUDING PRARALLEL DATABASES, PARALLEL IMPLEMENTATION OF NEURAL NETWORKS, PARALLEL IMAGE AND SPEECH PROCESSING, DISTRIBUTED AI AND EXPERTSYSTEMS AND OTHER PARALLEL APPLICATIONS.