HARDWARE-SOFTWARE CO-DESIGN SUPPORTS INTEGRATED ENGINEERING

PHASE I WILL EXPLORE NOVEL WAYS TO APPLY IMPROVED TECHNIQUES USING THE IEEE/ DOD STANDARD VHSIC HARDWARE DESCRIPTION LANGUAGE (VHDL) TO INTEGRATED ENGINEERING METHODS. IN PARTICULAR, IT WILL ENABLE HARDWARE AND SOFTWARE ENGINEERS TO COLLABORATE SIMULTANEOUSLY DURING DEVELOPMENT OF PARALLEL COMPUTING SYSTEMS. SOME SHORTCOMINGS OF VHDL HAVE BEEN OVERCOME BY THE DARPA QUEST PROJECT WITH DISTRIBUTING PROCESSING, WHICH HAS RESULTED IN SUBSTANTIAL REDUCTIONS IN THE TIME REQUIRED FOR VHDL SIMULATION AND SYNTHESIS. DISTRIBUTED PROCESSING OF VHDL DESCRIPTIONS IS ALSO BEING APPLIED TO AUTOMATIC TEST PATTERN GENERATION (ATPG). RESEARCH RESULTS FROM QUEST WILL BE INVESTIGATED. A MAJOR QUEST PARTICIPANT HAS PROPOSED A HARDWARE/SOFTWARE CO-DESIGN METHODOLOGY AND SEAMLESS TOOLSET THAT WILL BE DEVELOPED DURING PHASE II. THIS REVOLUTIONARY APPROACH WILL CAPTURE THE ALGORITHMS AND ARCHITECTURE OF A SYSTEM IN COMPOSITE HIGH-LEVEL VHDL MODELS. THE SYSTEM DESIGNER WILL GET RAPID FEEDBACK ON GROSS SYSTEM PERFORMANCE, RANGING FROM INSTRUCTION EXECUTION RATE AND NODE LOADING TO CHANGES IN ALGORITHMS OR ARCHITECTURE. PROOF OF CONCEPT WILL BE DEMONSTRATED DURING PHASE I. DURING PHASE II, THE TOOLS DESCRIBED IN PHASE I WILL BE DEVELOPED AND TESTED ON SAMPLE BEHAVIORAL AND STRUCTURAL VHDL MODELS OF A REAL DESIGN. COMMERCIAL SUPPLIERS OF VHDL DESIGN AUTOMATION TOOLS WILL BE IDENTIFIED AND EVALUATED FOR POTENTIAL PARTICIPATION IN THE PHASE III COMMERCIAL PRODUCT DEVELOPMENT. ANTICIPATED BENEFITS/POTENTIAL APPLICATIONS - EVALUATION OF THE PERFORMANCE OF HIGH-END DISTRIBUTED AND MASSIVELY PARALLEL COMPUTER PROCESSING SYSTEMS, SUCH AS THE TOUCHSTONE SIGMA AND QUEST PROJECTS. DECREASED TIME FOR DEVELOPMENT WILL RESULT FROM THE HARDWARE AND SOFTWARE CO-DESIGN.