Mitigation of Single Event Upset (SEU) by Virtual Redundancy in Design

Mitigation of Single Event Upset (SEU) to electronic devices and components has traditionally been and expensive problem to overcome. Dramatic improvements in electronics technology have rendered many prior SEU solutions ineffective and have created theneed for more advanced and innovative design tools. One of the more promising SEU solutions has been triple modular redundancy (TMR), where each processing and control circuit path is tripled and voted, such that when the outputs of the three circuitpaths are not the same, assuming single failure, the odd circuit is disregarded. Through an algorithmic approach, the same results can be obtained with single circuits by reusing idle clock cycles. Such an approach is far more economical, and morereliable, became there is no need to triple the circuit. Except for a small increase in area and power, a radiation hardened circuit can be produced for the same cost, area and power as a non rad-hard commercial component. The feasibility of developing atool named ART (Automatic Reconfiguration Tool) to create Virtual Redundancy in circuits was proven during Phase I, which included a demonstration at Space and Missile Defense Command in Huntsville, Alabama on September 12, 2000. Improve reliability andradiation tolerance of electronic devices efficiently through automated circuit reconfiguration in design phase. Specifically, the program will create a tool able to modify a completed design to add tolerance even to Single Event Upsets(SEU), theradiation effect which eludes most hardening techniques. The concept allows a completed design to be reconfigured with minimal added overhead to provide radiation tolerance and improved reliability through circuit design.