Scaleable Up to TeraFLOPS Super Grain Reconfigurable Paralalel DSP Technologies

We propose to design a processor for image processing applications that contains 4 to 64 reconfigurable DSPs/Neuro chips individually rated at 1.2-2.4 GigaFLOPS (10-20 BOPS) which will be capable of operating in parallel and providing 5-153 GigaFLOPS performance. These parallel rDSP chips with internal memories (4-16 MBytes/chips) will be capable of processing large sections of individual images. Nova Management has designed an innovative architecture for parallel systems operating in the range of 1.2 GigaFLOPS to several TeraFLOPS. This architecture is based upon a proven approach to DSP design with a a reconfigurable parallel systems architecture that was used by Dr. Medvedev, our Principal Investigator, in Russia. Dr. Medvedev managed the development and production of several generations of 32-640 parallel DSPs processors. These were used extensively for image processing and other applications. Our project which combines a Russian theoretical structure with US hardware technology will result in a high performance parallel workstations with performance of a least 20 GigaFLOPS, 2 Gigabytes of RAM processed images, contains 5,000 x 4,000 one byte pixels with resolution of 500 pixel per inch in real time and 500 more stored.