MULTICHANNEL CHARGE-SENSITIVE PREAMPLIFIERDEVELOPMENT USING

INCREASINGLY LARGE AND DENSELY PACKED SENSOR ARRAYS FOR CALORIMETERS, CERENKOV RING IMAGING, AND TIME PROJECTION CHAMBER SYSTEMS ARE PLACING MORE STRINGENT DEMANDS ON FRONT-END ELECTRONICS. THE NOISE PERFORMANCE AND DYNAMIC RANGE REQUIREMENTS OF THESE PREAMPLIFIERS ARE VERY STRINGENTAND TO SOME DEGREE MUST BE TAILORED TO THE APPLICATION. RECENT EXPERIENCE WITH LARGE SCALE HYBRIDIZATION OF SUCH PREAMPLIFIERS HAS SHOWN THE CLEAR LIMITATIONS OF THE HYBRID APPROACH IN SIZE, EXTERNAL CIRCUIT COMPLEXITY, AND COST. THIS PROJECT WILL STUDY THE FEASIBILITY OF DEVELOPING A MAJOR BUILDING BLOCK OR BLOCKS FOR A MULTICHANNEL PREAMPLIFIER USING WITH CURRENT VERY LARGE SCALE INTEGRATION(VLSI) TECHNOLOGY. SPECIAL PROBLEMS INCLUDE THE COUPLING OFAN EXTREMELY LOW INTEGRATION CAPACITANCE AND HIGH TRANSCONDUCTANCE FIELD-EFFECT TRANSISTOR FRONT END TO A BIPOLAR OR METAL OXIDE SEMICONDUCTOR MAIN SECTION, PLUS AN OPTIONAL BUFFER SECTION CAPABLE OF DRIVING A RELATIVELY HIGH CAPACITIVE LOAD, SUCH AS IS TYPICALLY FOUND IN BACK-END ELECTRONICS FOR WAVEFORM SAMPLING. A MAJOR HURDLE TO THE FURTHER INTEGRATION OF FRONT-END DATA ACQUISITION ELECTRONICS IS THE DEVELOPMENT OF HIGH DENSITY PREAMPLIFIERSAND ASSOCIATED CALIBRATION AND SHAPING ELECTRONICS. RECENT ADVANCES IN SAMPLING AND MULTIPLEXING ELECTRONICS CANNOT BE FULLY UTILIZED WITHOUT SIMILAR IMPROVEMENTS IN PREAMPLIFIER BUILDING BLOCKS. THE OBJECTIVE IS TO DESIGN MAJOR VLSI BLOCKS USING THE LATEST AVAILABLE CHIP TECHNOLOGIES THAT WILL COMBINE TRADITIONALLY DISCRETE PREAMPLIFIER AND SUPPORT CIRCUIT DESIGNS ONTO A COMMON BUILDING BLOCK. IT IS IMPORTANT TO EMPHASIZE THE REQUIREMENT FOR A SYSTEMS APPROACH TO THE PROBLEM, SINCE THE SUPPORT CIRCUITS CAN INTRODUCE CONSIDERABLE SYSTEMS COMPLEXITY IF THEY ARE NOT ALSO INCLUDED IN THE DESIGN.