SBIR/STTR Research Award
INTELLIGENT INPUT/OUTPUT SUBSYSTEM FOR CAMAC AND FASTBUS
Award amount
$183,000Program and phase
SBIR · Phase IIAward year
1987Award details
- Awarding agency
- National Science Foundation
- Branch
- Not reported
- Recipient company
- Aeon Systems Inc.
- Proposal award date
- Not reported
- Contract end date
- Not reported
- UEI
- Not reported
- Solicitation number
- Not reported
- Topic code
- Not reported
Research abstract
A MODULAR INPUT/OUTPUT SUBSYSTEM IS PROPOSED TO PROVIDE INTERFACE BETWEEN EXPERIMENTAL DATA ACQUISITION SYSTEMS USING THE CAMAC OR FASTBUS STANDARDS AND NEW-GENERATION DIGITAL EQUIPMENT CORPORATION MINICOMPUTERS. THE SYSTEM OFFERS A POTENTIAL TENFOLD INCREASE IN THE SPEED OF DATA ACQUISITION OVER CURRENT SYSTEMS. IT INCLUDES SUFFICIENT COMPUTER INTELLIGENCE TO MANAGE DATA TRANSFERS BETWEEN THE EXPERIMENT AND COMPUTER WITH MINIMUM INTERVENTION BY THE COMPUTER'S CENTRAL PROCESSOR. THE PROPOSED SYSTEM TAKES ADVANTAGE OF NEW INTERFACE BUS TECHNOLOGY TO PROVIDE WIDE BANDWIDTH COMMUNICATIONS AND REAL-TIME DATA PROCESSING CAPABILITY. DUE TO A UNIQUE RELATIONSHIP BETWEEN PROPOSER AND DEC, THE PROPOSED SYSTEM IS BELIEVED TO BE UNIQUE. THISPROPOSAL INCLUDES PRELIMINARY HARDWARE AND SOFTWARE DESIGN OF THE WHOLE SYSTEM AND OF ONE OF THE SYSTEM MODULES.
Technology keywords
Not reported