HIGH SPEED DATA ACQUISITION SYSTEM

A TECHNOLGY DEVELOPMENT IS PROPOSED WHICH WILL MAKE POSSIBLE DIGITIZERS OF 4-5 GS/S. CONSIDERABLE DESIGN WORK HAS ALREADY BEEN ACCOMPLISHED ON THE NEW TECHNOLOGY, BASED ON A EXTRAPOLATION OF EXISTING SHIP TECHNOLOGY WHICH HAS BEEN APPLIED TO A COMMERCIAL PRODUCT CAPABLE OF SAMPLE RATES UP TO 2 GS/S. THE PROPOSED DEVELOPMENT USES A NEW VERSION OF THE ANALOG SAMPLING ARRAY, A PATENTED DEVICE DEVELOPED FOR LARGE MULTICHANNEL PHYSICS EXPERIMENTS, AND COMMERCIALIZED UNDER LICENSE BY ANALYTAK, LTD., IN A MODULAR VME PACKAGE. THESE PRODUCTS CURRENTLY OFFER THE BEST PRICE-PERFORMANCE AVAILABLE AT BANDWIDTHS UP TO 350 MHZ. TRADEOFFS CAN BE MADE TO OPTIMIZE THE DESIGN TO THE SPECIFIC APPLICATION. THE TRADEOFFS INVOLVE RECORD LENGTH, SAMPLE RATE, NUMBER OF CHANNELS PER MODULE, DYNAMIC RANGE AND OVERALL ACCURACY. THE RECORD LENGTH IS DEFINED BY THE REQUIRED TIME WINDOW, WHICH IS IN TURN DEFINED BY THE DURATION OF THE EVENT OF INTEREST. THE FAST ANALOG MEMORY, TOGETHER WITH A HIGH AND LOW Z, GAIN SWITCHABLE PREAMPLIFIER OF AT LEAST 1 GHZ BANDWIDTH, AND ASSOCIATED TIMING CIRCUITS, WILL BE RELATIVELY EXPENSIVE; THEREFORE, THE UNIT WILL BE DESIGNED TO ACCOMMODATE TRADEOFFS TO OPTIMIZE PERFORMANCE VERSUS COST. A DESIRED TARGET IS AT LEAST 10 BITS OF DYNAMIC RANGE, 12 BITS DIGITIZING RESOLUTION, AND 6 EFFECTIVE BITS AT 750 MHZ INPUT FREQUENCY.