BUSLESS PARALLEL COMPUTER MEMORY ACCESSING SCHEME

RESEARCH ON A NOVEL PARALLEL COMPUTER MEMORY ACCESSING SCHEME IS PROPOSED IN ANSWER TO THE COMPUTER INDUSTRIES DRASTIC NEED FOR AN ACCESSING MECHANISM WHICH ALLOWS AN UNLIMITED NUMBER OF PROCESSORS TO SIMULTANEOUSLY READ AND WRITE TO A CENTRAL MEMORY IN FRACTIONS OF A MICROSECOND PER CYCLE. THE PROPOSED SYSTEM CONSISTS OF A BUSLESS PARALLEL ARCHITECTURE WHICH WILL ALLOW SIMULTANEOUS PARALLEL COMMUNICATION BETWEEN AN UNLIMITED NUMBER OF PROCESSORS AND/OR A GLOBAL MEMORY. THE PROPOSED SYSTEM WILL PROVIDE A SIGNIFICANT LEAP IN TECHNOLOGY AND WILL CRUCIAL TO THE INTERNATIONAL RACE TO BUILD THE NEXT GENERATION COMPUTER. THE KEY STRUCTURAL ELEMENT OF THE ACCESSING SCHEME WILL BE MODELED, FABRICATED, AND TESTED TO DETERMINE SIGNIFICANT OPERATING PARAMETERS. THE RESULTS OF THE TESTS WILL BE USED TO DETERMINE COMMERCIAL VIABILITY.