Novel Synthesis of Fluorinated Parylenes for Low-K Interlayer Dielectric Applications in Submicron ICs

As IC manufacturers pursue larger wafer sizes and smaller device features (0.25 um), the interlayer dielectric material becomes critical . Current interlayer dielectric materials, inorganic oxides and spin-coated polymeric materials, have serious deficiencies (e.g.,k >3, water absorption, and spin coating defects). This has led IC manufacturers to search for low-k($6000/lb) has hampered commercialization. Phase I will demonstrate a novel, cost effeclive syntheses for fluennated palylenes to be deposited by CVD to form low-k intellayer dielecl rics. The procedure uses direct modification of relatively inexpensive and commercially available parylenes as the basis for the preparation, avoiding the typically low yielding multi-step synthesis. The work will demonstrate that new fluorinated parylenes can be deposited in a CVD reactor now under development by a major semiconductor equipment manufacturer and confirm that the deposited coatings have the properties required for use in IC devices. The Phase II will optimize the preparation and CVD processing of selected fluorinated parylenes to increase yields, reduce costs, and improve device performance. If a suitable material can be developed, a major IC manufacturer projects coating 10,000 wafers per month within 1.5 years. It has since become apparent that other major IC producers are wanting to implement a similar "dry" coating process for polymer dielectrics. Semiconductor equipment manufacturers are, in fact, already responding to this need by introducing prototype parylene deposition reactors for wafer coating.