NANOMETER-SIZE STEP HEIGHT TEST STRUCTURES

MCNC PROPOSES A FEASIBILITY STUDY AND EVALUATION OF THREE PROMISING APPROACHES TO THE FABRICATION OF SURFACE TEST STRUCTURES ON SILICON. SURFACE FEATURES ON THE FIRST STRUCTURE WILL BE PRODUCED BY CONTROLLABLY ETCHING THERMALLYGROWN OXIDES. FEATURES ON THE SECOND WILL BE MADE BY ETCHING PIEZOELECTRIC THIN FILMS. USING THE PIEZOELECTRIC FILM AS PART OF A CAPACITOR, STEP-HEIGHT CAN BE VARIED AND PROVIDE FOR INTERNAL CALIBRATION. FEATURES ON THE THIRD STRUCTURE WILL BE FORMED BY ION-INDUCED SURFACE ROUGHENING. PHASE 1 WILL FOCUS ON EVALUATING THE TECHNICAL CHALLENGES AND COSTS OF FABRICATING EACH STRUCTURE. THE FABRICATION PARAMETERS TO BE EVALUATED ARE: (1) LITHOGRAPHIC PATTERNING;2) ETCHING AN OXIDE WITH ANGSTROM PRECISION AND ACCURACY; 3) DEPOSITING A PIEZOELECTRIC THIN FILM; 4) ETCHING A PIEZOELECTRIC THIN FILM; 5) ESTABLISHING THE SURFACE ROUGHNESS FOR GIVEN SPUTTER PARAMETERS; AND 6) FINDING A SUITABLE METAL OVERCOATING. IDENTIFICATION AND KNOWLEDGE OFTHE TECHNICAL DIFFICULTIES IN EACH OF THESE APPROACHES IN PHASE 1 WILL PERMIT THE PROPOSAL OF A PHASE 2 PROGRAM WITH HIGH CONFIDENCE IN TECHNICAL SUCCESS. PHASE 2 WILL FOCUS ONFABRICATING PROTOTYPE STRUCTURE(S) DEEMED MOST ECONOMICALLY FEASIBLE AND MOST LIKELY TO MEET ALL DOC PERFORMANCE REQUIREMENTS, ASSURING A SOUND BASIS FOR COMMERCIALIZATION.