A HIGH-SPEED DIFFERENTIAL CMOS LOGIC CIRCUIT FOR VLSI APPLI-CATIONS

THE MAIN OBJECTIVE OF THE OVERALL PROPOSAL (PHASE I AND PHASE II) IS TO STUDY AND DETERMINE THE FEASIBILITY OF A NOVEL DIFFERENTIAL CMOS LOGIC CIRCUIT CAPABLE OF OPERATING ONE ORDER OF MAGNITUDE FASTER THAN THE LOGIC CIRCUITS PRESENTLY USED IN VLSI APPLICATIONS> THE RESEARCH EFFORT PROPOSED FOR PHASE I IS DIVIDED IN THREE PARTS: (1) A SYSTEMATIC STUDY TO UNDERSTAND IN DETAIL HOW OTHER CIRCUITS SUCH AS THOSE USED IN STATIC CMOS MEMORIES ACCOMLISH HIGH OPERATING SPEEDS(2) A FEASIBILITY STUDY OF A NOVEL LOGIC CIRCUIT THAT OP- ERATES DIFFERENTIALLY WITH PRECHARGEING TO HALF OF THE SUP- PLY VOLTAGE AND EMPLOYS AN ASYNCHRONOUS SENSE LATCH, AND (3)A COMPARATIVE STUDY AND EVALUATION OF THREE 32-BIT ADDERS, ONE IMPLEMENTED WITH THE PROPOSED INNOVATIVE LOGIC CIRCUIT AND THE OTHER TWO WITH COMPETING CIRCUITS. THE SPEED OF THE THREE ADDERS WILL BE CALCULATED BY CIRCUIT SIMULATION (SPICEWILL BE ESTIMATED BASED ON THE TOTAL NUMBERS OF TRANSISTORS USED IN EACH OF THE ADDERS. THE ANTICIPATED RESULTS ARE T THAT THE 32-BIT ADDER DESIGNED WITH THE PROPOSED LOGIC CIR- CUIT WILL OPERATE APPROXIMATELY ONE ORDER OF MAGNITUDE FAST-ER THAN THE OTHER ADDERS. THE INCREASE IN THE LAYOUT AREA FOR THE PROPOSED CIRCUIT IS ESTIMATED AT ABOUT ONE THIRD OF CURRENTLY USED CIRCUITS IN VLSI DESIGN. ESSENTIAL INPUT FOR ANY COMPUTER SIMULATION INVESTIGATION. SIGNAL PROCESSOR FOR COMMERICAL AND SPCECRAFT.