SBIR/STTR Research Award
Computer Architecture for Extremely Rapid Processing
Award amount
$59,430Program and phase
SBIR · Phase IAward year
1996Award details
- Awarding agency
- Department of Defense
- Branch
- Missile Defense Agency
- Recipient company
- Nova Management, Inc.
- Proposal award date
- Not reported
- Contract end date
- Not reported
- UEI
- Not reported
- Solicitation number
- Not reported
- Topic code
- Not reported
Research abstract
We propose to develop an advanced processor that will contain 4 to 64 reconfigurable DSPs/Neuro chips individually rated at 1.2-2.4 GigaFLOPS (10-20 BOPS) capable of operating in parallel and providing 5-153 GigaFLOPS performance for optical signal processing and other advanced application areas. These parallel rDSP chips possess large associated internal memories (4-16 MBytes/chips) to support the processing of large sections of individual images. Nova Management has a design approach for developing parallel systems in the range of 1.2 GigaFLOPs to several TeraFLOPs. Dr. Medvedev, Principal Investigator, has designed similar systems in Russia containing 32-640 parallel DSPs. The system we propose combines Russian design theory with US hardware. The resulting machine will be capable of performance of at least 20 GigaFLOPs with Gigabytes of RAM.
Technology keywords
Not reported