RAPID PROTOTYPING USING SILICON COMPLICATION AND PROGRAMMABLE LOGIC DEVICES

IT HAS BEEN SHOWN THAT HARDWARE EMULATORS ENJOY A PERFORMANCE ADVANTAGE OF APPROXIMATELY THREE TO SIX ORDERS OF MAGNITUDE OVER SOFTWARE SIMULATORS. DESIGNERS WHO ARE ENGAGED IN THE DESIGN OF REAL-TIME EMBEDDED COMPUTER SYSTEMS COULD GREATLY BENEFIT FROM THE PERFORMANCE ADVANTAGE OF HARDWARE-BASED RAPID PROTOTYPING. OUR APPROACH INVOLVES AN INNOVATIVE WAY OF COMBINING TWO NEW AND EMERGING TECHNOLOGIES, SILICON COMPILATION AND PROGRAMMABLE LOGIC DEVICES (PLDS). IN THE VERY NEAR FUTURE, PLDS CONTAINING 10,000 EQUIVALENT GATES WILL BE COMMERCIALLY AVAILABLE. THE AVAILABILITY OF SUCH DEVICES IN CONJUNCTION WITH SILICON COMPILATION TECHNOLOGY LEADS TO NEW POSSIBILITIES IN RAPID PROTOTYPING OF DIGITAL SYSTEMS. THE GOAL OF OUR RESEARCH AND DEVELOPMENT EFFORT IS TO PRODUCE A SILICON COMPILER WITH A RETARGETABLE BACK END WHICH CAN SUPPORT RAPID PROTOTYPING UTILIZING VERY LARGE PLDS. THE COMPILER WILL ALSO SUPPORT GATE ARRAY AND STANDARD CELL DESIGN SO THAT THE DESIGN CAN QUICKLY AND EASILY BE MOVED INTO COST-EFFECTIVE VOLUME PRODUCTION.