A 250 MHZ, CMOS, STANDARD CELL LIBRARY FOR THE IMPLEMENTATION OF PIPELINED SYSTEMS WITH LOW POWER DISSIPATION

THE OBJECTIVE OF THE PHASE I ADVANCED DEVELOPMENT EFFORT ARE TO DESIGN A HIGHSPEED, LOW-POWER, STANDARD CELL LIBRARY WHICH IS ANTICIPATED TO PROVIDE A FACTOR OF 3 INCREASE IN THE PERFORMANCE-TO-POWER RATIO OF CMOS DIGITAL INTEGRATED CIRCUITS. A NOVEL CMOS CIRCUIT, CALLED PDL (PIPELINED DIFFERENTIAL LOGIC), WAS DEVELOPED AND SEVERAL DESIGNS WERE FABRICATED FOR THE PAST 3 YEARS. ALTHOUGH, PDL INTEGRATED CIRCUITS OPERATED AT 1 GHZ, UNFORTUNATELY, THAT WAS ACCOMPLISHED WITH A 5 V POWER SUPPLY AND CONSEQUENTLY AT THE EXPENSE OF HIGH POWER DISSIPATION. THE INNOVATIVENESS OF THE PROPOSED RESEARCH IS BASED ON THE RECOGNITION THAT A STANDARD CELL LIBRARY EMPLOYING THE PDL CIRCUITS CAN BE DEVELOPED TO OPERATE WITH A CLOCK FREQUENCY OF 250 MHZ AND ONLY A 2 V POWER SUPPLY. BECAUSE AT HIGH FREQUENCY MOST OF THE POWER DISSIPATED IS DYNAMIC, A REDUCTION OF THE POWER SUPPLY VOLTAGE FROM 5 V TO ONLY 2 V WILL REDUCE THE DYNAMIC POWER DISSIPATION BY A FACTOR OF 9. A PIPELINED FLOATING POINT ADDER WILL SERVE AS A TEST VEHICLE TO DETERMINE BY SIMULATION (PHASE I) AND TO VALIDATE EXPERIMENTALLY (PHASE II) THAT A 250 MFLOP THROUGHPUT AND LESS THAN 3 W POWER DISSIPATION CAN BE ACHIEVED WITH A COMBINATION OF PDL CIRCUITS, 2 V POWER SUPPLY, AND 0.8 FM CMOS FABRICATION PROCESS. A SUCCESSFUL COMPLETION OF THE PROPOSED ADVANCED DEVELOPMENT WILL ENABLE US TO DEVELOP AND MARKET SEVERAL PIPELINED VLSI CHIPS SUCH AS FLOATING-POINT UNITS, DIGITAL FILTERS, AND DIGITAL CORRELATORS WITH A SIGNIFICANTLY HIGHER PERFORMANCE-TOCOST RATIO THAN THAT OF EXISTING PRODUCTS.