AN INNOVATIVE APPROACH TO PRODUCE MULTI-MEGARAD HARD ELECTRONIC DEVICES FOR SPACEBORNE APPLICATIONS HAS BEEN PROPOSED, WHEREBY JUNCTION FIELD EFFECT TRANSISTORS (JFET) ARE DEVELOPED USING SILICON-ONINSULATOR (SOI) TECHNOLOGY.

AN INNOVATIVE APPROACH TO PRODUCE MULTI-MEGARAD HARD ELECTRONIC DEVICES FOR SPACEBORNE APPLICATIONS HAS BEEN PROPOSED, WHEREBY JUNCTION FIELD EFFECT TRANSISTORS (JFET) ARE DEVELOPED USING SILICON-ONINSULATOR (SOI) TECHNOLOGY. THE MULTIMEGARAD HARDNESS IS DERIVED FROM THE 'BURIED' CHANNEL OF THE JFET DEVICES AND THE REDUCTION OF ELECTROMIGRATION OF TRAPPED AND INDUCED CHARGES OF THE WELL-MATCHED SILICON/OXIDE INTERFACE OF THE SILICON-ON-INSULATOR WAFER, FABRICATED BY OXYGEN IMPLANT OF SILICON WAFER. THIS PROPOSED EFFORT IS PHASE 1 OF A 3-PHASE PROGRAM, CONCEIVED SPECIFICALLY TO EXPLOIT THE EMERGING SOI TECHNOLOGY BASED ON THE SILICON-IMPLANT-OXIDE (SIMOX) PROCESS. THE MAJOR TASKS FOR PHASE I ARE: ANALYSIS AND MODELING OF COMPLEMENTARY JFET (CJFET) DEVICES AND CIRCUITS.